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(R)
ISL22416
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet September 9, 2009 FN6227.2
Low Noise, Low Power, SPI(R) Bus, 128 Taps
The ISL22416 integrates a single digitally controlled potentiometer (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up, the device recalls the contents of the DCP's IVR to the WR. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 128 resistor taps * SPI serial interface * Non-volatile storage of wiper position * Wiper resistance: 70 typical @ VCC = 3.3V * Shutdown mode * Shutdown current 5A max * Power supply: 2.7V to 5.5V * 50k or 10k total resistance * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T +55C * 10 Ld MSOP and 10 Ld TDFN package * Pb-free (RoHS compliant)
Pinout
ISL22416 (10 LD MSOP) TOP VIEW
SCK SDO SDI CS SHDN 1 2 3 4 5 10 9 8 7 6 VCC RH RW RL GND SCK SDO SDI CS SHDN
ISL22416 (10 LD TDFN) TOP VIEW
1O 2 3 4 5 10 VCC 9 RH 8 RW 7 RL 6 GND
Ordering Information
PART NUMBER (Note) ISL22416UFU10Z* ISL22416UFRT10Z* ISL22416WFU10Z* ISL22416WFRT10Z* PART MARKING 416UZ 416U 416WZ 416W RESISTANCE OPTION (k) 50 50 10 10 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 10 Ld MSOP 10 Ld 3x3 TDFN 10 Ld MSOP 10 Ld 3x3 TDFN PKG. DWG. # M10.118 L10.3x3B M10.118 L10.3x3B
*Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22416 Block Diagram
VCC
SCK SDO SDI CS SPI INTERFACE
POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH
WR
RW
SHDN
IVR NON-VOLATILE REGISTER
RL
GND
Pin Descriptions
MSOP/TDFN PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL SCK SDO SDI CS SHDN GND RL RW RH VCC SPI interface clock input Push-pull/Open Drain Data Output of the SPI serial interface Data Input of the SPI serial interface Chip Select active low input Shutdown active low input Device ground pin "Low" terminal of DCP "Wiper" terminal of DCP "High" terminal of DCP Power supply pin DESCRIPTION
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Lead MSOP (Note 2). . . . . . . . . . . . 162 N/A 10 Lead TDFN (Notes 2, 3) . . . . . . . . . 74 7 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40C to +125C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -1V for all pins. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Analog Specifications
Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEST CONDITIONS W option U option MIN TYP (Note 4) 10 50 -20 50 80 70 0 10/10/25 Voltage at pin from GND to VCC Monotonic over all tap positions, W and U option Monotonic over all tap positions, W and U option W option U option -1 -0.5 0 0 -5 -2 1 0.5 -1 -1 4 0.1 1 200 VCC +20 MAX UNIT k k % ppm/C (Note 18) ppm/C (Note 18) V pF A
SYMBOL RTOTAL
PARAMETER RH to RL Resistance RH to RL Resistance Tolerance End-to-End Temperature Coefficient
W and U option W option U option
RW VRH, VRL CH/CL/CW (Note 18) ILkgDCP INL (Note 9) DNL (Note 8) ZSerror (Note 6) FSerror (Note 7)
Wiper Resistance VRH and VRL Terminal Voltages Potentiometer Capacitance Leakage on DCP Pins
VCC = 3.3V, wiper current = VCC/RTOTAL VRH and VRL to GND
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) Integral Non-linearity Differential Non-linearity Zero-scale Error 1 0.5 5 2 0 0 LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) ppm/C
Full-scale Error
W option U option DCP register set to 40 hex for W and U option
Ratiometric Temperature Coefficient TCV (Note 10, 18)
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ISL22416
Analog Specifications
Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEST CONDITIONS MIN TYP (Note 4) MAX UNIT
SYMBOL
PARAMETER
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) RDNL (Note 13) Integral Non-linearity DCP register set between 10 hex and 7F hex; monotonic over all tap positions; W and U option W option U option Roffset (Note 12) Offset W option U option -1 1 MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11)
Differential Non-linearity
-1 -0.5 0 0 1 0.5
1 0.5 5 2
Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (Volatile Write/Read) VCC Supply Current (Non-volatile Write/Read) VCC Current (Standby) TEST CONDITIONS fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) VCC = +5.5V @ +85C, SPI interface in standby state VCC = +5.5V @ +125C, SPI interface in standby state VCC = +3.6V @ +85C, SPI interface in standby state VCC = +3.6V @ +125C, SPI interface in standby state ISD VCC Current (Shutdown) VCC = +5.5V @ +85C, SPI interface in standby state VCC = +5.5V @ +125C, SPI interface in standby state VCC = +3.6V @ +85C, SPI interface in standby state VCC = +3.6V @ +125C, SPI interface in standby state ILkgDig tWRT (Note 18) tShdnRec (Note 18) Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to VCC, SDI, SDO and CS SDO is inactive Wiper Response Time DCP Recall Time from Shutdown Mode Wiper Response Time after SPI write to WR register From rising edge of SHDN signal to wiper stored position and RH connection SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection VPOR VCC Ramp Power-on Recall Voltage VCC Ramp Rate Minimum VCC at which memory recall occurs 2.0 0.2 -1 1.5 1.5 1.5 2.6 MIN TYP (Note 4) MAX 0.5 3 5 7 3 5 3 5 2 4 1 UNIT mA mA A A A A A A A A A s s s V V/ms
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Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL tD PARAMETER Power-up Delay TEST CONDITIONS VCC above VPOR, to DCP Initial Value Register recall completed, and SPI Interface in standby state MIN TYP (Note 4) MAX 3 UNIT ms
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 16) Non-volatile Write Cycle Time Temperature T +55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECIFICATIONS VIL VIH Hysteresis VOL Rpu (Note 17) Cpin (Note 18) fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tCS NOTES: 4. Typical values are for TA = +25C and 3.3V supply voltage. 5. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)127 - VCC]/LSB. SHDN, SCK, SDI, and CS Input Buffer LOW Voltage SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage SHDN, SCK, SDI, and CS Input Buffer Hysteresis SDO Output Buffer LOW Voltage SDO Pull-up Resistor Off-chip SHDN, SCK, SDI, SDO and CS Pin Capacitance SPI Frequency SPI Clock Cycle Time SPI Clock High Time SPI Clock Low Time Lead Time Lag Time SDI, SCK and CS Input Setup Time SDI, SCK and CS Input Hold Time SDI, SCK and CS Input Rise Time SDI, SCK and CS Input Fall Time SDO Output Disable Time SDO Output Valid Time SDO Output Hold Time SDO Output Rise Time SDO Output Fall Time CS Deselect Time Rpu = 2k, Cbus = 30pF Rpu = 2k, Cbus = 30pF 2 0 60 60 200 100 100 250 250 50 50 10 10 0 20 100 350 IOL = 4mA Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz -0.3 0.7*VCC 0.05* VCC 0 0.4 2 10 5 0.3*VCC VCC + 0.3 V V V V k pF MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
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NOTES: (Continued) 8. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 9. INL = [V(RW)i - (i * LSB) - V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 10. TC V = --------------------------------------------------------------------------------------------- x -------------------- for i = 16 to 127 decimal, T = -40C to 125C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = |RW127 - RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 12. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 13. RDNL = (RWi - RWi-1)/MI -1, for i = 1 to 127. 14. RINL = [RWi - (MI * i) - RW0]/MI, for i = 1 to 127. 6 [ Max ( Ri ) - Min ( Ri ) ] 10 15. TC = --------------------------------------------------------------- x ---------------- for i = 16 to 127, T = -40C to 125C. Max( ) is the maximum value of the resistance and Min ( ) is R [ Max ( Ri ) + Min ( Ri ) ] 2 165C the minimum value of the resistance over the temperature range. 16. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 17. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 18. Limits should be considered typical and are not production tested.
Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SDI MSB tH tCYC ... tWH ... tLAG
tWL
tFI LSB
tRI
SDO
HIGH IMPEDANCE
Output Timing
CS
SCK tV SDO MSB tHO
... tDIS ... LSB
SDI
ADDR
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ISL22416
XDCP Timing (for All Load Instructions)
CS tWC
SCK
... tWRT ...
SDI
MSB
LSB
VW
SDO
HIGH IMPEDANCE
Typical Performance Curves
100 90 WIPER RESISITANCE () 80 70 ISB (A) 60 50 40 30 20 10 0 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) VCC = 3.3V, T = +20C VCC = 3.3V, T = -40C 1.0 0.8 0.6 0.4 0.2 0 2.7 T = +25C T = +125C VCC = 3.3V, T = +125C 1.4 1.2
3.2
3.7
4.2 VCC (V)
4.7
5.2
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FIGURE 2. STANDBY ICC vs VCC
0.2 T = +25C VCC = 2.7V 0.1 DNL (LSB) INL (LSB)
0.2 T = +25C 0.1
VCC = 2.7V
0
0
-0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL)
-0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
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ISL22416 Typical Performance Curves
1.3 10k 1.1 0.9 ZSERROR (LSB) 0.7 0.5 0.3 0.1 -0.1 -0.3 -40 -20 0 20 50k VCC = 2.7V VCC = 5.5V ZSERROR (LSB) -0.3 VCC = 2.7V 50k VCC = 5.5V
(Continued)
0.0
-0.6
-0.9 10k -1.2
40
60
80
100
120
-1.5 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSERROR vs TEMPERATURE
FIGURE 6. FSERROR vs TEMPERATURE
0.4 T = +25C 0.2 DNL (LSB) VCC = 5.5V
0.4 T = +25C 0.2 INL (LSB) VCC = 5.5V
0
0
-0.2
-0.2
-0.4 VCC = 2.7V -0.6 16 36 56 76 96 116
-0.4 VCC = 2.7V -0.6 16 36 56 76 96 TAP POSITION (DECIMAL) 116
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
1.0 END TO END RTOTAL CHANGE (%)
105 90
0.5 VCC = 2.7V 0.0 VCC = 5.5V 10k -0.5 50k TCv (ppm/C)
75 60 45 30 15 50k 10k
-1.0 -40
0 -20 0 20 40 60 80 100 120 16 36 56 76 96 TEMPERATURE (C) TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
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ISL22416 Typical Performance Curves
(Continued)
INPUT 300 250 TCr (ppm/C) 200 150 50k 100 50 0 16 10k WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5k OUTPUT
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
SCL
SIGNAL AT WIPER (WIPER UNLOADED)
SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Description
Potentiometer Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL22416 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.
SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RH and shorts RW to RL. When SHDN is returned to logic high, the previous latch settings put RW at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation.
RH
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
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Bus Interface Pins
SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22416, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22416 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22416 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the SPI serial interface as described in the following sections.
Memory Description
The ISL22416 contains one non-volatile 7-bit register, known as the Initial Value Register (IVR), volatile 7-bit Wiper Register (WR), and volatile 8-bit Access Control Register (ACR). The memory map is shown in Table 1. The non-volatile register (IVR) at address 0, contain initial wiper position and volatile registers (WR) contain current wiper position.
TABLE 1. MEMORY MAP ADDRESS 2 1 0 IVR NON-VOLATILE -- Reserved WR VOLATILE ACR
Principles of Operation
The ISL22416 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value.
The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR<7>) determines whether the access is to wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7 6 SHDN 5 WIP
4 0
3 0
2 0
1 0
0 0
BIT NAME VOL
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal
If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR<6>) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR<5>) is read only bit. It indicates that non-volatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the WR or ACR while WIP bit is 1.
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Shutdown Mode
The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3.
TABLE 3. SHUTDOWN MODE SHDN PIN High Low High Low SHDN BIT 1 1 0 0 MODE Normal operation Shutdown Shutdown Shutdown
by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to address 0 (WR), the byte at address 2 (ACR<7>) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to "Memory Description" on page 10 and Figure 16. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms.
Read Operation
A read operation to the ISL22416 is a three byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed by "dummy" Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again.
SPI Serial Interface
The ISL22416 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22416. SCK and CS lines are controlled by the host or master. The ISL22416 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first.
Applications Information
Communicating with ISL22416
Communication with ISL22416 proceeds using SPI interface through the ACR (address 10b), IVR (address 00b) and WR (address 00b) registers. The wiper of the potentiometer is controlled by the WR register. Writes and reads can be made directly to this register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 10b to 1. The non-volatile IVR stores the power up value of the wiper. IVR is accessible when MSB bit at address 10b is set to 0. Writing a new value to the IVR register will set a new power up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. Reading from the IVR will not change the WR, if its contents are different.
Protocol Conventions
The first byte sent to the ISL22416 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0.
TABLE 4. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 0 (LSB)
The next byte sent to the ISL22416 contains the instruction and register pointer information. The four MSBs are the instruction and two LSBs are register address (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT 7 I3 6 I2 5 I1 4 I0 3 0 2 0 1 R1 0 R0
There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation There are only two registers address possible for this DCP. If the R1, R0 bits are zero, then the read or write is to either the IVR or the WR register (depends of VOL bit at ACR). If the R1 bit is 1 and R0 bit is 0, then the operation is on the ACR.
Write Operation
A Write operation to the ISL22416 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed
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CS
SCK
SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0 0 D6 D5 D4 D3 D2 D1 D0
FIGURE 16. THREE BYTE WRITE SEQUENCE
CS
SCK
SDI 0 SDO 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0
DON'T CARE
D6 D5 D4
D3
D2
D1 D0
FIGURE 17. THREE BYTE READ SEQUENCE
Examples
A. Writing to the IVR
This sequence will write a new value (77h) to the IVR (non-volatile): Set the ACR (Addr 02h) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte
010100001100001001000000 (Sent to DI)
B. Reading from the WR
This sequence will read the value from the WR (volatile): Write to ACR first to access the WR Send the ID byte, Instruction Byte, then the Data byte
010100001100001011000000 (Sent to DI)
Read the data from WR (Addr 00h) Send the ID byte, Instruction Byte, then Read the Data byte
Set the IVR (Addr 00h) to 77h Send the ID byte, Instruction Byte, then the Data byte
010100001100000001110111 (Sent to DI)
0101000010110000xxxxxxxx (Out on DO)
12
FN6227.2 September 9, 2009
ISL22416 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
13
FN6227.2 September 9, 2009
ISL22416 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L10.3x3B
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A3 b D 0.18
6 INDEX AREA TOP VIEW B
0.25 3.00 BSC
0.30
5, 8 -
D2 E
// 0.10 C 0.08 C
2.23
2.38 3.00 BSC
2.48
7, 8 -
E2 e k
1.49
1.64 0.50 BSC
1.74
7, 8 -
A C SEATING PLANE SIDE VIEW A3
0.20 0.30
0.40 10 5
0.50
8 2 3 Rev. 0 2/06
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6227.2 September 9, 2009

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